1. Field of Invention
The present invention relates to semiconductor non-volatile memory. More particularly, the present invention relates to a non-volatile memory with selection gate.
2. Description of Related Art
Flash memory device allows multiple-time erase and program operation inside system. As a result, flash memory is suitable to many of advance hand-held digital apparatuses, such as solid state disks, cellar phones, digital cameras, digital movie cameras, digital voice recorders, and personal digital assistant (PDA), that are demanding a low-cost, high-density, low-power-consumption, highly reliable file memory.
Basically, data flash memory has two typical cell structures. One is double poly NAND type memory cell with poly l as floating gate to store charges; and the other one is single poly SONOS cell with SiN as storage node. A conventional NAND flash includes numerous strings of series connected N-channel transistor. Device operation of NAND flash utilizes channel Fowler-Nordheim (FN) mechanism for programming and erasing, and cell size for the NAND type flash memory cell is around 4–5F2, here F represents a critical dimension used in semiconductor fabrication as a dimension reference for describing cell size.
On the other hand, conventional SONOS technology is a NOR type flash memory with buried N+ structure. FIG. 1 is a cross-sectional view, schematically illustrating a conventional SONOS flash memory. Device operation of SONOS cell is adopted channel hot carriers for programming and B—B hot holes for erase. FIG. 2 is top view, schematically illustrating the layout of the memory cell with respect to FIG. 1. In FIG. 1 and FIG. 2, the N-well 102 and the P-well 104 are formed in the substrate 100, such as a P-type substrate. Since the whole flash memory includes memory region and the logic region, the various wells are formed to have the CMOS device. The memory cells are formed in the T(triple)P-well 104 as can be understood by the ordinary skilled artisans. For this kind of flash memory, the bit lines BL0, BL1, . . . , BLm 106 are formed in the substrate with strip doped regions. This kind of design for the bit lines is also called the buried bit line design. FIG. 2 only shows the layout for the bit lines 106 and the word lines 110. The charge storage is achieved by the oxide 108a/nitride 108b/oxide 108c (O/N/O) structure layer 108. The word line 110 also serves as the necessary gate.
The operation mechanisms for above cell design in programming, reading and erasing operations are shown in FIG. 3. The word line (WL) is also the gate electrode. The adjacent two bit lines serve as the source/drain (S/D) region in the substrate. The oxide/nitride/oxide (O/N/O) structured layer is between the gate electrode and the substrate, in which the nitride layer is used to store the charges. Due to the charges in the nitride layer basically not moving, the injected charges can be localized in the nitride layer. Therefore, according to the voltages applied on the bit lines, for example for the programming operation at the top two drawings. For the operation shown in left drawing, due to the hot electrons, desired charges are stored in the nitride layer, in which the charges are localized at the one side. However, for the reversed direction shown the right drawing, the charges are stored in the nitride at the left side. Then, for the reading operation, according to the reading direction, the two sides can be separated read. The stored charges change the threshold voltage, so that the stored binary data can be sensed. The erasing operation is to inject the band-to-band (B—B) holes to the nitride layer to neutralize the electrons, so as to erase. Basically, The programming operation is to change the threshold voltage from low to high, and the erasing operation is to change the threshold voltage from high back to low. The operation should be well known by the skilled artisans and the detailed description is skipped.
However, the conventional SONOS flash memory has the disadvantages. As shown in FIG. 3, charges in nitride layer may laterally diffuse between twin bits in SONOS cell. This is because the straight nitride layer still has insufficient power to localize the store charges. When some of the stored charges drift to the other side, at which no charge is expected, the bit error would occur. In addition, the hot carriers for programming consumes a larger current that can't support page mode programming.